library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity Mux16x1 is
port(
  
  Ins 	 	 : in bus16x32;
  Op		 : in std_logic_vector(3 downto 0);
  Outs  	 : out std_logic_vector(31 downto 0)
);
end Mux16x1;

architecture rtl of Mux16x1 is
  begin
    Outs <= 	Ins(to_integer(unsigned(Op)));
end architecture rtl;
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